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External Publications
- Jos van Eijndhoven,
Creating safe multi-threaded applications in C++11,
ACCU Conference, Bristol, UK, Apr. 2014.
- J.T.J. van Eijndhoven,
Application parallelization for multi-core Android devices,
Presentation at Bits and Chips 2012 Embedded Systems,
s hertogenbosch, Netherlands, Nov. 8, 2012.
- Jos van Eijndhoven,
Application parallelization for multi-core Android devices,
ARM TechCon, Santa Clara, California, Oct. 2012.
- J.T.J. van Eijndhoven,
Application analysis for parallelization on multi-core devices,
HiPEAC Computing Systems,
Ghent, Belgium, Oct. 16, 2012.
- J.T.J. van Eijndhoven,
Parallelization of C programs through dependency analysis,
ACM Symposium on High-Performance Parallel and Distributed Computing,
Delft, the Netherlands, June 20, 2012.
- J.T.J. van Eijndhoven,
Mapping applications into MPSoC: concurrency & communication,
Tutorial presentation at DATE 2012,
Dresden, Germany, Mar. 12, 2012
- A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Compositional, efficient caches for a chip multi-processor,
proc. Design, Automation and Test in Europe (DATE'06), Vol. 1,
Munich, Germany, Mar. 6-10, 2006
- Jos van Eijndhoven, Jan Hoogerbrugge, Jayram M.N., Paul Stravers, Andrei Terechko,
Cache-coherent heterogeneous multiprocessing as basis for streaming applications
In: Dynamic and Robust Streaming in and between Connected Consumer-Electronic Devices,
Philips Research Book Series, Vol. 3, Peter van der Stok (Ed.),
ISBN-101-4020-3453-9, Springer, pp. 61-80, 2005
- Clara Otero Perez, Martijn Rutten, Liesbeth Steffens, Jos van Eijndhoven, Paul Stravers,
Resource reservations in shared-memory multiprocessor SOCs
In: Dynamic and Robust Streaming in and between Connected Consumer-Electronic Devices,
Philips Research Book Series, Vol. 3, Peter van der Stok (Ed.),
ISBN-101-4020-3453-9, Springer, pp. 109-138, 2005
- Mihai Sima, Sorin Cotofana, Jos T.J. van Eijndhoven, Stamatis Vassiliadis, Kees Vissers,
IEEE-compliant IDCT on FPGA-Augmented TriMedia
In: Journal of VLSI Signal Processing, Vol. 39, Springer, pp. 195-212, 2005
- Abraham K. Riemens, Josephus T.J. van Eijndhoven,
Integrated circuit comprising a measurement unit for measuring utilization,
International patent WO-2005/041056 A2, May 6, 2005
- Frans W. Sijstermans, Jos van Eijndhoven,
Rounding operations in computer processor
United States Patent US6889242/B1, May 3, 2005
- Kornelis A. Vissers, Marcel J.A. Tromp, Jos van Eijndhoven,
Replacing VLIW operation with
equivalent operation requiring fewer issue slots
United States Patent US6886091/B1, Apr. 26, 2005
- G. Kuzmanov, S. Vassiliadis, J.T.J. van Eijndhoven,
Hardwired MPEG-4 repetitive padding
IEEE Transactions on Multimedia, Vol. 7, Issue 2, pp. 261-268, Apr. 2005
- Pieter van der Wolf, Josephus T.J. van Eijndhoven,
Data processing system,
International patent WO-2005/026964 A2, March 24, 2005
- A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Compositional memory systems for multimedia communicating tasks,
proc. Design, Automation and Test in Europe (DATE'05), Vol. 2, pp. 932-937,
Munich, Germany, Mar. 7-11, 2005
- Xing Li, Jos van Eijndhoven, Ben Juurlink,
3D-TV Rendering on a Multiprocessor System on a Chip,
proc. ProRISC 2004, pp. 271-282, ISBN 90-73461-43-X,
Veldhoven, the Netherlands, Nov. 25-26, 2004
- A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Cache Partitioning Options for Compositional Multimedia Applications,
proc. ProRISC 2004, pp. 86-90, ISBN 90-73461-43-X,
Veldhoven, the Netherlands, Nov. 25-26, 2004
- Mihai Sima, Sorin D. Cotofana, Stamatis Vassiliadis, Jos T.J. van Eijndhoven, Kees A. Vissers,
Pel Reconstruction on FPGA-Augmented TriMedia
IEEE Trans. on Very Large Scale Integration (VLSI) Systems,
Vol. 12, No. 6, pp. 622-635, June 2004
-
Martijn J. Rutten, Jos T.J. van Eijndhoven, Evert-Jan D. Pol,
"Caching Techniques for Multi-Processor Streaming Architectures",
Workshop on Media and Signal processors for Embedded Systems and SoCs (MASES),
Washington D.C., USA, Sept. 22, 2004
- Josephus T.J. van Eijndhoven, Martijn J. Rutten, Evert-Jan D. Pol,
Data processing system with prefetching means,
International patent WO-2004/079489 A2, Sept. 16, 2004
- Josephus T.J. van Eijndhoven, Martijn J. Rutten, Evert-Jan D. Pol,
Data processing system with cache optimised for processing dataflow applications,
International patent WO-2004/079488 A2, Sept. 16, 2004
- Martijn J. Rutten, Josephus T.J. van Eijndhoven, Evert-Jan D. Pol,
Data processing system having a plurality of processing elements,
a method of controlling a data processing system having
a plurality of processing elements,
International patent WO-2004/077206 A2, Sept. 10, 2004
-
Martijn Rutten, Om Prakash Gangwal, Jos van Eijndhoven, Egbert Jaspers, Evert-jan Pol,
"Application Design trajectory towards Reusable Coprocessors, MPEG Case study"
Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia),
Stockholm, Sweden, Sept. 6-7, 2004
- Josephus T.J. van Eijndhoven,
Data processing system and a method for operating the same,
International patent WO-2004/031962 A2, April 15, 2004
- Erik B. van der Tol, Gerben J. Hekstra, Evert-Jan D. Pol, Josephus T.J. van Eijndhoven,
A method of communicating data within a coder,
International patent WO-2004/017641 A1, Febr. 26, 2004
-
A.M. Molnos, M.J.M. Heijligers, S.D. Cotofana, J.T.J. van Eijndhoven,
Compositional memory systems for data intensive applications,
Proc. Design, Automation and Test in Europe Conference (DATE2004),
Vol. 1, pp. 728-729, Feb. 16-20, 2004
- Martijn J. Rutten, Josephus T.J. van Eijndhoven, Evert J. Pol,
Data processing system having multiple processors, a task scheduler
for a data processing system having multiple processors and
a corresponding method for task scheduling,
International patent WO-03/052597 A2, June 26, 2003
- Josephus T.J. van Eijndhoven, Evert J. Pol, Martijn J. Rutten,
Method for data processing in a multi-processor data processing system
and a corresponding data processing system,
International patent WO-03/052589 A2, June 26, 2003
- Josephus T.J. van Eijndhoven, Evert J. Pol, Martijn J. Rutten,
Data processing system having multiple processors and a communication means
in a data processing system having multiple processors,
International patent WO-03/052586 A2, June 26, 2003
- Josephus T.J. van Eijndhoven, Evert J. Pol, Martijn J. Rutten, Om P. Gangwal,
Data processing system,
International patent WO-03/052588 A2, June 26, 2003
-
Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T.J. van Eijndhoven,
Color Space Conversion for
MPEG decoding on FPGA-augmented TriMedia processor,
Proc. IEEE 14th Int. conf. on Application-specific Systems, Architectures, and Processors
(ASAP 2003), The Hague, The Netherlands, June 24-26, 2003
-
Andrei Terechko, Erwan Le Thenaff, Manish Garg, Jos van Eijndhoven, Henk Corporaal,
Inter-cluster Communication Models for Clustered VLIW Processors,
Nineth Int. Symp. on High Performance Computer Architecture (HPCA-9),
Anaheim, California, Febr. 8-12, 2003
- Rohini Krishnan, O.P. Gangwal, Jos v. Eijndhoven, Anshul Kumar "Design
of a 2D DCT/IDCT application specific VLIW processor supporting scaled and
sub-sampled blocks", Proc. 16th int. conf. on VLSI Design 2003, New
delhi, India, Jan. 4-8, 2003
- Mihai Sima, Stamatis Vassiliadis, Jos T.J. van Eijndhoven, Sorin Cotofana,
"Y'UV-to-R'G'B'
Color Space Conversion on FPGA-augmented TriMedia-32 Processor", Proc.
of the Workshop on Circuits, Systems and Signal Processing (ProRISC 2002),
ISBN 90-73461-33-2, Veldhoven, The Netherlands, pp. 465-470, Nov. 28-29, 2002
- Manvi Agarwal, S.K. Nandy, J. v. Eijndhoven, S. Balakrishnan, "Speculative
Trace Scheduling in VLIW Processors" Proc. IEEE Int. conf. On Comp.
Design (ICCD 2002) IEEE Comp. Soc. Press, Freiburg, Germany, pp. 408-413,
Sept. 16-18, 2002
- Manvi Agarwal, S.K. Nandy, J. v. Eijndhoven, S. Balakrishnan, "Multithreaded
Architectural Support for Speculative Trace Scheduling in VLIW
Processors", Proc. 15th Brazilian Symp. on Integrated Circuit Design
(SBCCI 2002), Porto Allegre, Brazil, Sept. 9-14, 2002
- Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T.J. van Eijndhoven,
Kees A. Vissers, "Field-Programmable
Custom Computing Machines. A Taxonomy", Proc. of the Field-Programmable
Logic and Applications (FPL2002), Montpellier, France, September 2-4, 2002
In: "Field-Programmable Logic and Applications: Reconfigurable Computing
Is Going Mainstream", Eds. M. Glesner, P. Zipf, M. Renovell, Lect. Notes in
Comp. Sc., vol. 2438, isbn
3-540-44108-5, Springer, pp. 79-88, 2002
- Martijn J. Rutten, Jos T.J. van Eijndhoven, Evert-Jan D. Pol, Egbert G.T.
Jaspers, Pieter van der Wolf, Om Prakash Gangwal, Adwin Timmer, Eclipse:
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IEEE Design and Test of Computers vol. 19, no. 4, pp. 39-50, IEEE Comp.
Soc. Press, July-Aug. 2002
- Martijn J. Rutten, Jos T.J. van Eijndhoven, Evert-Jan D. Pol,
Robust
media processing in a flexible and cost-effective network of multi-tasking
coprocessors, Proc. Euromicro Conf. on Real-Time Systems, Estes
Park, Colorado, USA, June 19-21, 2002
- Manvi Agarwal, S.K. Nandy, Jos van Eijndhoven, S. Balakrishnan,
On the Benefits of Speculative Trace
Scheduling in VLIW Processors, Proc. of Parallel and Distributed Processing
Techniques and Applications (PDPTA'02),Las Vegas, USA, June 2002.
- Josephus T.J. Van Eijndhoven, Franciscus W. Sijstermans, "Data
processing device and method of computing the costine transform of a
matrix", U.S. patent 6,397,235 B1, Assignee: Koninklijke Philips
Electronics N.V., Eindhoven, The Netherlands, granted May 28, 2002
- Martijn J. Rutten, Jos T.J. van Eijndhoven, Evert-Jan D. Pol, Design
of Multi-Tasking Coprocessor Control for Eclipse, Proc. 10th Int. Symp.
on Hardware/Software Codesign (CODES 2002), Vienna, Austria, May 6-8, 2002
- Martijn J. Rutten, Jos T.J. van Eijndhoven, Evert-Jan D. Pol, Egbert G.T.
Jaspers, Pieter van der Wolf, Om Prakash Gangwal, Adwin Timmer, Eclipse:
Heterogeneous Multiprocessor Architecture for Flexible Media Processing
Proc. Workshop on Parallel and Distributed Computing in Image Processing,
Video Processing, and Multimedia (PDVIM 2002) Fort Lauderdale, Florida,
USA, Apr. 15, 2002
- Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T.J. van Eijndhoven,
Kees A. Vissers, "MPEG-compliant
Entropy Decoding on FPGA-augmented TriMedia/CPU64" Proceedings of the
IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM
2002), Napa Valley, California, April 21-24, 2002.
- Pieter van der Wolf, Wido Kruijtzer, Jos van Eijndhoven, "System-Level
Design of Embedded Media Systems", full-day tutorial
abstract
in Proc. 7th Asia and South Pacific Design Automation Conf. and 15th Int.
Conf. on VLSI design (ASP-DAC / VLSI Design 2002), Bangalore, pp. 14-15,
India, 7-11 Jan. 2002
- Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T.J. van Eijndhoven,
``Variable-Length
Decoder Implemented on a TriMedia/CPU64 Reconfigurable Functional Unit'',
Proc. of the Workshop on Circuits, Systems and Signal Processing (ProRISC
2001), Veldhoven, The Netherlands, Nov. 2001
- G.Kuzmanov, S.Vassiliadis, Jos T.J. van Eijndhoven, "A
Padding Processor for MPEG-4", Proc. 12th Annual Workshop on Circuits,
Systems, and Signal Processing (ProRISC2001), Veldhoven, The Netherlands,
29-30 Nov. 2001
- G.Kuzmanov, S.Vassiliadis, Jos T.J. van Eijndhoven, "An
Implementation of the MPEG-4 ACQ Function", Proc. 12th Annual Workshop
on Circuits, Systems, and Signal Processing (ProRISC2001), Veldhoven, The
Netherlands, 29-30 Nov. 2001
- G.Kuzmanov, S.Vassiliadis, Jos T.J. van Eijndhoven, "MPEG-4
Addressing and ACQ Function", Proc. of the Second Workshop on Embedded
Systems and Software (PROGRESS 2001), Veldhoven, The Netherlands, Oct.
2001
- Mihai Sima, Sorin Cotofana, Jos T.J. van Eijndhoven, Stamatis Vassiliadis,
"An
8-Point IDCT Computing Resource Implemented on a TriMedia/CPU64 Reconfigurable
Functional Unit", Proc. of the Second Workshop on Embedded Systems and
Software (PROGRESS 2001), Veldhoven, The Netherlands, Oct. 2001
- Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T.J. van Eijndhoven,
Kees A. Vissers, ``MPEG
Macroblock Parsing and Pel Reconstruction on an FPGA-augmented TriMedia
Processor'', Proc. of the Int. Conference on Computer Design (ICCD
2001), Best Paper Award, Austin, Texas, Sept. 2001, pp. 425-430
- Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T.J. van Eijndhoven,
Kees A. Vissers, ``A
Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study'',
Proc. of the Workshop on System Architecture Modeling and Simulation (SAMOS
2001), Samos, Greece, July 2001
In: "Embedded Processor Design
Challenges", Eds. E.F. Deprettere , S. Vassiliadis, Lect. Notes in Comp.
Sc. vol. 2268, isbn
3-540-43322-8, Springer, pp. 224-241, 2002
- G.Kuzmanov, S.Vassiliadis, J. van Eijndhoven, "A
2D Addressing Mode for Multimedia Applications", Proc. Workshop on
System Architecture Modeling and Simulation (SAMOS 2001), Samos, Greece,
July 2001,
In: "Embedded Processor Design Challenges", Eds. E.F.
Deprettere , S. Vassiliadis, Lect. Notes in Comp. Sc. vol. 2268, isbn
3-540-43322-8, Springer, pp. 291-306, 2002
- A. Terechko, J.T.J. van Eijndhoven, E.J. Pol, "PRMDL:
a Machine Description Language for Clustered VLIW Architectures". Design,
Automation and Test in Europe Conference (DATE 2001), Munich, Germany, March
2001, pp 821.
- Mihai Sima, Sorin Cotofana, Jos T.J. van Eijndhoven, Stamatis Vassiliadis,
Kees A. Vissers, "An
8x8 IDCT Implementation on an FPGA-augmented TriMedia", in: proc. of
IEEE Symp. on Field-Programmable Custom Computing Machines (FCCM 2001),
Rohnert Park, California, April-May 2001
- Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana, Jos T.J. van Eijndhoven,
Kees A. Vissers, "A
Taxonomy of Custom Computing Machines", in: proc. of Progress workshop
on Embedded Systems (Progress 2000), J. P. veen (Ed.), ISBN 90-73461-22-7,
Technology Foundation STW, Oct 13, 2000, Utrecht, The Netherlands, pp. 87-93
- A.D. Pimentel, P. van der Wolf, E.F. Deprettere, L.O. Herzberger, J.T.J.
van Eijndhoven, S. Vassiliadis, "The
Artemis Architecture Workbench", in: proc. of Progress workshop on
Embedded Systems (Progress 2000), J. P. veen (Ed.), ISBN 90-73461-22-7,
Technology Foundation STW, Oct 13, 2000, Utrecht, The Netherlands, pp. 53-62
- Jos T. Van Eijndhoven, Gerrit A. Slavenburg, Selliah Rathnam, "VLIW
Processor has different functional units operating on commands of different
widths", U.S. Patent 6,076,154, Assignee: U.S. Philips Corporation,
New York, granted Jun. 13, 2000
- J.T.J. van Eijndhoven, F.W. Sijstermans, K.A. Vissers, E.J.D. Pol, M.J.A.
Tromp, P. Struik, R.H.J. Bloks, P. van der Wolf, A.D. Pimentel, H.P.E.
Vranken, "TriMedia
CPU64 Architecture", (invited paper), (ppt
session sheets), proc. Int. Conf. on Computer Design (ICCD99),
10-13 Oct. 1999, Austin, Texas, pp. 586-592
- E.J.D. Pol, B.J.M. Aarts, J.T.J. van Eijndhoven, P. Struik, F.W.
Sijstermans, M.J.A. Tromp, J.W. van de Waerdt, P. van der Wolf, "TriMedia
CPU64 Application Development Environment", (invited paper) (ppt
session sheets), proc. Int. Conf. on Computer Design (ICCD99),
10-13 Oct. 1999, Austin, Texas, pp. 593-598
- Josephus T.J. van Eijndhoven, Franciscus W. Sijstermans,
Data procesing device and method of computing the cosine transform of a matrix"
International patent WO-99/48025 A2, Sept. 23, 1999
- J.T.J. van Eijndhoven, F.W. Sijstermans, "Novel
Multimedia Instruction Capabilities in VLIW media processors", (ppt
sheets), proc. Hot Chips 10, 16-18 Aug. 1998, Palo Alto, Cal., pp.
163-173
- B.J.M. Aarts, A. Augusteijn, E.H.L Aarts, J.T.J. van Eijndhoven,
"programming VLIW Architectures with Super Operations", Multimedia Hardware
Architectures 1998, proc. of SPIE, 29-30 Jan. 1998, San Jose, Cal., pp.
79-85
- Gerrit A. Slavenburg, Jos T. van Eijndhoven, Selliah Rathnam,
"VLIW
Processor processes commands of different widths",
International patent WO-99/36845 A2, July 22, 1999
- L.C.V. dos Santos, J.T.J. van Eijndhoven, J.A.G. Jess, "Combining
code motion and scheduling", Proc. ProRisc Workshop on Circuits,
Systems and Signal Processing 1996, Mierlo, the Netherlands, November
1996, pp. 279-284.
- L.C.V. dos Santos, M.J.M. Heijligers, C.A.J. van Eijk, J.T.J. van
Eijndhoven, J.A.G. Jess, "A
constructive method for exploiting code motion", Proc. ISSS 96, La
Jolla, CA, USA, November 1996, pp. 51-56. ISBN 0-8186-7563-2.
- A.H. Timmer, J.T.J. van Eijndhoven, J.A.G. Jess, "Conflict
modelling and instruction scheduling in code generation for in-house DSP
cores", Synopsis university program symposium Shaping the Future of
High-Level Design, Köln, Germany, Oct. 1995
- J.T.J. van Eijndhoven; "CMOS
cell generation for Logic Synthesis", in: proc. 1st int. conf. on ASIC
(ASICON 94); Wang Yangyuan (Ed.); Beijing, China, Oct 18-21, 1994, pp.
75-78; Electr. Ind. Publ. House, Wanshou Rd., Beijing, China.
- E.P. Huijbregts, J.T.J. v. Eijndhoven, J.A.G. Jess, "On
design Rule Correct Maze Routing" In: Proc. Eur. Design and Test Conf.
(EDAC-ETC-EUROASIC); Paris, France, Feb 28 - Mar 3, 1994, pp. 407-411;
IEEE Comp. Soc. Press, 1994
- J.T.J. van Eijndhoven, J. Jess, J.P. Brage, "Behavioural
Specification for Synthesis", In : Application-Driven Architecture
Synthesis; F. Catthoor, L. Svensson (Eds.), Kluwer Ac. Publ., 1993, pp.
23-46.
- M.J.M. Heijligers, H.M.A.M. Arts, J.T.J. van Eijndhoven, H.A. Hilderink,
J.A.G. Jess, W.J.M. Philipsen, A.H. Timmer, "The
New Eindhoven Architectural synthesis Toolbox", Proc. of the
ProRISC/IEEE benelux workshop on circ. syst. and signal proc.; March
24-25, Houthalen, Belgium, pp. 71-75, Eds: J.P. Veen, M.J. de Ket, STW,
Utrecht, March 1993,
- J.T.J. van Eijndhoven; "A
Data Flow Graph Exchange Standard", Proc. Workshop of the ESPRIT 2260
SPRITE project: Interactive Silicon Compilation for High Performance
Integrated Systems; pp. 1-27; (Ed. P. Pype), IMEC, Leuven (Be.), May 1992.
- J.T.J. van Eijndhoven, L. Stok; "A
Data Flow Graph Exchange Standard", Proc. of the European Conference on
Design Automation; Brussels (Be.), pp. 193-199, IEEE Comp. Soc. Press,
March 1992.
- J.P. Brage, J.T.J. van Eijndhoven, K. O'Brien, P. Poechm\o'u\(..'ller; "The
Data Flow Graph in the ASCIS project", Third Periodic Progress Report,
BRA 3261 (ASCIS): Behavioural Synthesis, Partitioning, and Architectural
Optimization for Complex Systems on Silicon, Part 2, pp. 1-22, (Ed. L.
Svensson), IMEC, Leuven (Be.), March 1992.
- J.T.J. van Eijndhoven, G.G. de Jong, L. stok; "The
ASCIS data flow graph: Semantics and textual format", as deliverable
tue/m24/a1/3 in: Second periodic Progress Report, BRA 3281 (ASCIS):
Behavioural Synthesis, Partitioning, and Architectural Optimization for
Complex Systems on Silicon, Part 2, pp. 1-54, (Ed. L. Svensson), IMEC,
Leuven (Be.), june 1991.
- J.T.J. van Eijndhoven, G.G. de Jong, L. stok; The
ASCIS data flow graph: Semantics and textual format; EUT Report
91-E-251, ISBN 90-6144-251-6, Eindhoven Univ. of Technology, The
Netherlands, June 1991.
- H.M.A.M. Arts, L. Stok, J.T.J. van Eijndhovpublications/en, "Flexible
block multiplier generation", Readers Digest of Technical Papers of the
Int. Conf. on Comp. Aided Design; pp. 106-110; Santa Clara (Cal.), Nov.
1991
- J.T.J. van Eijndhoven; "EDIF
Level-2 to level-0 translation", Proc. Fourth European EDIF Forum;
pp. 170-175; Warrington, England, 11-12 oct. 1990
- F. Catthoor, B. Courtois, H. De Man, E. Deprettere, P. Dewilde, M.
Glesner, C. Goutis, J. Jess, J. Madsen, K. O'Brien, O. Olesen, I. Park, L.
Philipson, P. Quinton, J, Vandewalle, J. v. Eijndhoven, N. Wehn, L. Svensson
(Ed.); "Novel
Architecture Design Methodologies and Synthesis Strategies for Future ASIC
Design", Proc. of the Nordic Silicon Compiler (NORSILC) Seminar-90;
pp. 1.0 - 1.9.; Lund, Sweden, Oct 30 - Nov 1, 1990
- J.T.J. van Eijndhoven, M.T. van Stiphout, H.W. Buurman, "Multirate
Integration in a Direct Simulation Method", Proc. of The European
Design Automation Conference (EDAC); pp. 306-309; Glasgow, Scotland, march
12-15, 1990
- M.T. van Stiphout, J.T.J. van Eijndhoven, H.W. Buurman, "PLATO:
A New Piecewise Linear Simulation Tool", Proc. of The European Design
Automation Conference (EDAC); pp. 235-239; Glasgow, Scotland, march 12-15,
1990
- L.P.P.P. van Ginneken, J.T.J. van Eijndhoven, J.A.H.C.M. Brouwers; "Doubly
Folded Transistor Matrix Layout" Proc. IEEE Int. Conf. on Comp. Aided
Design (ICCAD); pp. 134-137; Santa Clara, California, nov. 7-10, 1988.
- Eijndhoven, J.T.J. van; Ginneken, L.P.P. van; Teeffelen, P. van; Deckers,
Th.; "Soft
Macro Cell Generation By Two Dimensional Folding", Proceedings
International Symposium on Circuits And Systems, Espoo, Finland, june 7-9,
1988.
- Eijndhoven, J.T.J. van; Stiphout, M.T. van, "Latency
exploitation in circuit simulation by sparse matrix techniques"
Proceedings International Symposium on Circuits And Systems, Espoo,
Finland, june 7-9, 1988.
- Eijndhoven, J.T.J. van; "Piecewise Linear Analysis"; In: "Analog
Circuits: Computer Aided Analysis and Diagnosis" T. Ozawa (ed.), pp.
65-92, Marcel Dekker inc., New York, march 1988.
- Brayton, R.K.; Camposano, R.; De Micheli, G.; Otten R.H.J.M.; Eijndhoven,
J.T.J. van; "The Yorktown Silicon Compiler System"; In: "Silicon
Compilation", Dan Gajski (Ed.), Addison-Wesley Publ. comp.; jan. 1988
- Eijndhoven, J.T.J. van; Camposano, R.; "Combined synthesis of control
logic and datapath"; Proceedings International Conference on Computer Aided
Design, pp. 327-329, Santa Clara, California; november 9-12, 1987.
- Camposano, R.; Eijndhoven, J.T.J. van; "Partitioning a Design in
Structural Synthesis"; Proceedings International Conference on Circuit
Design, Rye Brook, New York; oktober 5-8, 1987.
- Eijndhoven, J.T.J. van; Stiphout, M.T. van; "Design and Evaluation of a
new piecewise linear simulator"; proceedings European Conference on Circuit
Theory and Design 1987, pp. 107-112 (invited paper), Paris; sept. 1-4,
1987.
- Brayton, R.K.; Camposano, R.; De Micheli, G.; Otten R.H.J.M.; Eijndhoven,
J.T.J. van; "The Yorktown Silicon Compiler System"; IBM Research Report RC
12500 (#56205); IBM T.J. Watson Research Center, Yorktown Heights, New
York, dec. 1986.
- Eijndhoven, J.T.J. van; "Solving the linear complementarity problem in
circuit simulation"; SIAM J. Control and Optimization, vol. 24, No. 5,
pp.1050-1062, sept. 1986
- Lodder, A; Stiphout, M. van; Eijndhoven, J.T.J. van; "ESCHER: Eindhoven
SCHematic EditoR; reference manual" EUT report 86-E-157, Eindhoven
University of Technology, Dept. of Electrical Engineering, Eindhoven, The
Netherlands, feb 1986.
- Eijndhoven, J.T.J. van; "The Piecewise Linear Simulator" "The
Integrated Circuit Design Book"; P. Dewilde (ed.), Delft University Press,
The Netherlands, pp.4.1-4.59, jan. 1986.
- Lodder, A; Stiphout, M. van; Eijndhoven, J.T.J. van; "The Eindhoven
Schematic Editor" "The Integrated Circuit Design Book"; P. Dewilde
(ed.), Delft University Press, The Netherlands, pp.1.61-1.68, jan. 1986.
- Eijndhoven, J.T.J. van; "A piecewise linear simulator for large scale
integrated circuits"; PhD Thesis, Eindhoven Univ. of Tech., Eindhoven,
The Netherlands, dec. 1984.
- Eijndhoven,J.T.J. van; Jess,J.A.G.; "Mixed mode mixed level analysis with
PWL systems"; Proc 17th Int. Symp. on Circuits And Systems, Montreal,
Canada, may 7-10 1984, pp.1377-1380. (invited paper)
- Eijndhoven,J.T.J. van; Jess,J.A.G.; "State analysis of large piecewise
linear systems"; Proc. IEEE Int. Conf. on Computer Design: VLSI in
Computers, Port Chester, N.Y., 31 okt-2 nov 1983, pp.503-506.
- Brooijmans,J.A.M.; Eijndhoven,J.T.J. van; Jess,J.A.G.; "A new multilevel
simulation program for large systems based on piecewise linear models";
Proc. 6th European Conf. on Circuit Theory and Design, Stuttgart,
Germany, 6-8 sept. 1983. Chairman: E. Lueder, Co-chairman: E. Gleissner.
Berlin: VDE-Verlag, 1983, pp.426-428.
- J.T.J. van Eijndhoven,J.T.J. van; "The modelling of mos-transistors for a
piecewise linear circuit simulator", (invited paper) Proc. 16th Int. Symp.
on Circuits And Systems, Newport Beach, California, may 2-4 1983,
pp.748-751
- J.T.J. van Eijndhoven,J.T.J. van; Bokhoven,W.M.G. van; "Piecewise linear
modelling in the simulation of electronic networks"; Proc. 15th Int. Symp.
on Circuits And Systems, Rome, Italy, may 5-8 1982, pp.1206-1209
- J.T.J. van Eijndhoven, J.A.G. Jess, "The solution of large piecewise
linear systems" Proc. 15th Int. Symp. on Circuits And Systems, Rome,
Italy, may 5-8 1982, pp.597-600
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